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Routing a differential pair
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Isaac Marino Bavaresco
Mon, 17 Sep 12 21:03:53 +0000
Dear All,


I'm designing a board with two ARM devices that will communicate via
High-Speed USB. One of them will be the host and the other will be a
device. Between them there will be a High-Speed USB Hub chip (a Renesas
μPD720114) with three more USB Type A ports.

This is my first design above 100MHz (the USB runs at 480Mbps) and I'm
really afraid of the transmission-line effects.

The USB differential lines must have 45ohm impedance relative to the
plane (Z0) and 90ohm differential impedance (Zd).

Assuming er = 4.2, trace thickness = 35μm (1oz):

If I use 0.2mm dielectric thickness, then each track must be 0,395mm
wide (a reasonable width) to achieve 45ohm impedance to the plane, but
then to achieve 90ohm differential impedance, the track separation must
be 2.384mm, which is unreasonable.

In reality I would like to use a two-sided board, thus the dielectric
thickness would be 1.6mm.
That increases the track width to 3.469mm to achieve 45ohm impedance to
the plane, which is (very) unrealistic.


I have here one old PCI USB expansion board that uses the VIA VT6202
chipset and it is built as a two-sided board with tracks on top layer
and a cross-hatched plane on the bottom layer.
Its tracks are 0.16mm wide and 0.24mm apart. That gives Z0=149.6ohm and
Zd=174.8ohm. Most important, the board *WORKS* (or used to work years ago).



Am I doing the maths wrong? Where is my mistake?

I'm tempted to copy the VT6202 routing parameters to my board. Does it
have any chances of working?


Best regards,

Isaac

1 replies folowing

Tue, 18 Sep 12 08:16:43 +0000
> The USB differential lines must have 45ohm impedance relative to the plane (Z0) and
> 90ohm differential impedance (Zd).
>
> Assuming er = 4.2, trace thickness = 35μm (1oz):
>
> If I use 0.2mm dielectric thickness, then each track must be 0,395mm wide (a
> reasonable width) to achieve 45ohm impedance to the plane, but then to achieve 90ohm
> differential impedance, the track separation must be 2.384mm, which is unreasonable.
>
> In reality I would like to use a two-sided board, thus the dielectric thickness
> would be 1.6mm.
> That increases the track width to 3.469mm to achieve 45ohm impedance to the plane,
> which is (very) unrealistic.
>
>
> I have here one old PCI USB expansion board that uses the VIA VT6202 chipset and it
> is built as a two-sided board with tracks on top layer and a cross-hatched plane on
> the bottom layer.
> Its tracks are 0.16mm wide and 0.24mm apart. That gives Z0=149.6ohm and Zd=174.8ohm.
> Most important, the board *WORKS* (or used to work years ago).
>
>
>
> Am I doing the maths wrong? Where is my mistake?
>
> I'm tempted to copy the VT6202 routing parameters to my board. Does it have any
> chances of working?


It might, but I wouldn't bet on it. Did that board really operate at 480MB/s, or 12MB/s?

As to getting the right trace parameters, do what we do for our high speed Spacewire traces, lay the board out, and send it off to your board house identifying your critical traces and their required impedance, and ask them for the trace width and spacing for their board stack up. They should come back with the appropriate figures for you to use. For what you are doing you may not want to go to the additional expense of them verifying track impedances during manufacture, depending on how long they are, and how well you match the lengths of the two traces in a differential pair.